演算法與計算理論學會

Association of Algorithm and Computation Theory

研討會訊息公告

主題
Workshop on Algorithms for Electronic Design Automation
主辦單位
演算法與計算理論學會
協辦單位
IEEE CEDA Taipei Chapter
時間
2016年10月14日(五)13:30~17:00
地點
清華大學資訊電機館地下室演講廳
參考文件

Algorithms in Design for Manufacturability.pptx

FromEEtoCS-Oct-14-2016.pdf
Logic Optimization using Logic Implication and its application to Verification.pptx

流程

13:30~13:40

開場致詞

 

13:40~14:40

Talk 1
Problem Solving Methods: from EE to CS (電機資訊解題之道)
Speaker:台灣大學電機工程學系 陳少傑教授
Abstract: In this talk, the speaker will give an overview of how Electrical Engineering (EE) engineers use Computer Science (CS) and mathematical techniques, such as graph theory and linear programming, to solve their problems. Majorly two EDA problems, VLSI physical design and circuit simulation, will be depicted as examples.


14:40~15:40
Talk 2
Logic Optimization using Logic Implication and its application to Verification
Speaker:清華大學資訊工程學系 王俊堯教授
Abstract: Node merging is a popular and effective logic restructuring technique that has recently been applied to minimize logic circuits. However, in the previous satis?ability (SAT)-based methods, the search for node mergers required trial-and-error validity checking of a potentially large set of candidate mergers. Here, we propose a new method, which directly identi?es node mergers using logic implications without any SAT solving calls. To enhance the node-merging techniques on logic restructuring and optimization, we further propose a node addition and removal (NAR) approach. It works by adding a node into a circuit to replace an existing node and then removing the replaced node. We apply the node-merging and NAR approaches to circuit minimization as well as SAT-based bounded sequential equivalence checking (BSEC) to reduce the computation complexity of SAT solving.


15:40~16:00

茶敘


16:00~17:00

Talk 3
Development and Application of Algorithms in Design for Manufacturability
Speaker:台灣科技大學電機工程學系方劭云教授
Abstract: As semiconductor process reaches sub-10nm technology nodes, considerable circuit complexity and serious process variation cause increasing difficulty in integrated circuit manufacturing. In this talk, we will address different design challenges for advanced lithography technologies, such as layout decomposition in multiple patterning lithography, subfield scheduling in electron beam lithography, and template assignment in directed self-assembly. To improve manufacturability, optimization problems are formulated and sophisticated algorithms are developed, which will be introduced.